Aspects of the present invention relate generally to the field of data transmission and more specifically to differential signaling at the physical layer.
Conventionally, differential signaling provides for transmission of a single instance of information content from a driver to a receiver via a pair of transmitted signals having opposite state (e.g., data+ and data−). Differential signaling may be used in analog or digital systems and provides an efficient method of communication with low power dissipation and low susceptibility to electromagnetic interference. Differential signaling may be implemented at the physical layer using any of several standards including, for example, RS-422, USB, Serial ATA (SATA), FireWire, or HDMI.
Each of the various methods of implementing differential signaling may have different data transmission rates and output voltage specifications. For example, Low Voltage Differential Signaling (LVDS) provides a low power, high-speed transmission of data in the physical layer and is sometimes used in analog-to-digital converters and digital signal processors requiring high-speed data transmissions. A subLVDS driver is similar to LVDS, but with a smaller differential swing and a smaller common-mode voltage than a standard LVDS driver and is sometimes used in camera analog front-ends and image processors. For example, an LVDS driver may have a data rate up to 1.9 Gbps, a differential output swing of 350 mV and a common-mode voltage of 1.25V, whereas a subLVDS driver may have a data rate of 416 Mbps with a differential voltage swing of 150 mV and a fixed common-mode voltage of 0.9V.
In conventional LVDS and subLVDS drivers, the supply voltage is typically 2× the common-mode voltage. Thus, a conventional LVDS driver may have a fixed common-mode voltage of 1.25V with a supply voltage of 2.5V, and a subLVDS driver may have a common-mode voltage of 0.9V with a supply voltage of 1.8V. Because the ideal power supply for the system is not necessarily 2× the common-mode, a separate supply is often dedicated to the driver. As multiple supplies generally imply extra cost, board area, and additional circuit complexity, this can be undesirable. If current-mode techniques are used, using 2× the common-mode is more a convention than a requirement. However, since the trend is for lower system supply voltages, current-mode techniques can have significant headroom limitations. Voltage-mode techniques are well suited to low supply voltages, but conventional methods require a supply of 2× the common-mode voltage in order to have a balanced output impedance. Therefore while it is desirable to limit the number of supplies, it is often impractical using conventional methods.
FIG. 1 is a simplified circuit diagram illustrating components of a conventional current-mode driver 100 that may be used for differential signaling. In the example of FIG. 1, a current is driven through the circuit to implement a current-mode driver 100. As shown in FIG. 1, the current-mode driver 100 may include a pair of circuit paths each extending from a current source 105 to a current sink 106 and including respective output terminals 104a, 104b. Each circuit path may include a switch 101a, 101b extending between the respective output terminal 104a, 104b and the current source 105 and a switch 102a, 102b extending between the respective output terminal 104a, 104b and the current sink 106.
As shown in FIG. 1, the current-mode driver 100 may receive a pair of differential input signals D+ and D− and may output a pair of differential output signals OUT+ and OUT− in response. An input signal (say, D+) may be input to the switches 101a, 102a of a first path. Similarly, the other input signal D− may be input to the switches 101b, 102b of a second path. Thus, when a differential input signal is asserted to the current-mode driver 100, one of the input signals D+, D− will cause its associated switches to conduct a current through the termination resistor 107 to produce a fixed differential output voltage given by |v(OUT+)−v(OUT−)|. The common-mode voltage is given by (v(OUT+)+v(OUT−))/2, and may be set by a servo loop (not shown) or other method. Termination resistor 107 may be implemented separately from the current-mode driver 100, and a known or expected termination resistance may impact the design of the current-mode driver 100.
Conventional current-mode drivers, as the driver depicted in FIG. 1, may additionally require bias currents, bias current generators, and/or servo loops to operate properly. Additionally, with lower supply voltages, current-mode drivers may require larger output devices that can lead to increased supply/substrate noise due to their larger capacitance.
FIG. 2 is a simplified circuit diagram illustrating components of a conventional voltage-mode driver 200 that may be used for differential signaling. In the example of FIG. 2, rather than switching a current through the driver, the supply voltages VDD, VSS are switched to implement a voltage-mode driver 200. As shown in FIG. 2, the voltage-mode driver 200 may include a pair of circuit paths each extending between a pair of supply voltages (VDD, VSS) and including respective output terminals 204a, 204b. Each circuit path may include a switch 202a, 202b extending between the respective output terminal 204a, 204b and a first supply voltage VDD and a switch 203a, 203b extending between the respective output terminal 204a, 204b and the second supply voltage VSS. The voltage-mode driver 200 further may include resistors 201a, 201b coupled between each output terminal 204a, 204b and one of the supply voltages.
As shown in FIG. 2, the voltage-mode driver 200 may receive a pair of differential input signals D+ and D− and may output a pair of differential output signals OUT+ and OUT− in response. An input signal (say, D+) may be input to the switches 202b, 203b of a first path. Similarly, the other input signal D− may be input to the switches 202a, 203a of a second path. Thus, when an input signal is asserted to the voltage-mode driver 200, one of the input signals D+, D− will cause its associated switches to conduct, which produces signal voltages on the output terminals 204a, 204b. Termination resistor 207 may be implemented separately from the driver.
However, conventional voltage-mode drivers, as the driver depicted in FIG. 2, are generally designed for a balanced output impedance which means that resistor 201a equals resistor 201b. Otherwise, the two output states would have different common-mode voltages, which may result in electromagnetic interference (EMI). Additionally, an unbalanced impedance may cause common-mode to differential conversion in the presence of unwanted common-mode signals. If resistors 201a and 201b are equal, it forces the common-mode voltage to equal one-half the supply voltage. This implies (for example) a 2.5V power supply for LVDS, and a 1.8V power supply for subLVDS. Accordingly, it may be desirable to implement a high-speed, differential signaling driver in voltage-mode with a single supply voltage not equal to 2× the common-mode voltage.